This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-65025, filed on Mar. 11, 2002; the entire contents of which are incorporated herein by reference.
The present invention relates to a testing method at a high timing accuracy in the case of performing a test for selecting acceptable and unacceptable semiconductor integrated circuit devices (LSI) when evaluating characteristics thereof and mass-producing these devices. The present invention also relates to a semiconductor integrated circuit device applied to an adjustment of a timing skew, at a test signal interface with an exterior of the semiconductor integrated circuit device, a signal from a semiconductor testing apparatus etc. to a semiconductor integrated circuit Device Under Test (which will hereinafter be abbreviated to DUT) or a signal from the DUT to the semiconductor testing apparatus etc.
Over the recent years, in a test environment for judging in an evaluation test and in a mass-production test whether the higher-speed semiconductor integrated circuit is acceptable or unacceptable, there have been increasingly high demands for improving a timing accuracy of an input signal applied to the DUT and an output signal from the DUT. What requires a high accuracy is typically a high-speed interface circuit, an MPU executing clock signal-multiplication in internal PLL/DLL, a chip-to-chip/board-to-board high-speed data transfer and receipt, and so on.
Then, in the case of testing this type of semiconductor integrated circuit device at a real speed, there arises a problem that a timing skew between the signals in the semiconductor testing apparatus etc. is not allowable.
A first conventional method executed for obviating this problem is that calibration data up to a test head end included in the semiconductor testing apparatus as a system are corrected by use of electric wiring length data of a device board that is measured directly by an oscilloscope or by a TDR (Time Domain Reflectometry) measurement. The skew calibration up to the DUT end can be thereby attained.
The first conventional method is a method that has hitherto been widely generally conducted, but does not reach the timing accuracy demand level described above in terms of the timing accuracy. A reason for this is that timing data obtained by arithmetically calculation is not coincident with timing data obtained in an actual resting state where the semiconductor testing apparatus is actually connected to the device board. In this case, the timing data is calculated using electric wiring length measured in a way that propagates a signal at, for example, a test head end directly or up to a different measurement unit and an electric wiring length measured by use of an external measuring device such as the oscilloscope etc. as a single device board.
The main cause thereof is, it is considered, derived from discordance between an input waveform at the test head end and an input waveform when measuring by the single device board in the case of measuring by propagating the signal at the test heat end directly or up to the different measurement unit, and from mismatching of impedance at a connection point between the test head end and the device board.
A second conventional method is a calibration at the DUT end and involves performing a manual probing measurement using an external measuring device serving as a basis and a measurement in an automatic probing system. The second conventional method schemes to actualize a higher calibration than by the first conventional method described above.
If the number of pins increases in the manual probing, however, the precise probing that ensures a reproducibility can not be attained in such an environment that the worker properly replaces it at a site of the mass-production.
A third conventional method is a measurement using a short-circuiting device or a measurement of the electric wiring length based on the TDR method using an open-circuiting device. This method utilizes a reflection in a case where a signal transmitted with a fixed characteristic impedance showing zero or infinity of the characteristic impedance at the DUT end.
Those methods have a problem in which a fine adjustment of the characteristic impedance is, of course, hard to execute in the case of making the fine adjustment thereof on a transmission path as frequently done by a high-speed device, and an essentially required electric wiring length only on an outgoing path or a returning path because of different inclinations, different qualities and different frequency components of the signal waveforms on the outgoing path and the returning path.
According to one aspect of the invention, there is provided a semiconductor integrated circuit. device comprising:
a semiconductor substrate on which a semiconductor chip is provided;
a plurality of phase comparators, provided on said semiconductor substrate, with input signals to said semiconductor integrated circuit from outside serving as one inputs thereof; and
a variable delay circuit, provided on said semiconductor substrate, configured to adjust a timing of a reference clock signal which is used for a phase comparison;
wherein distributed reference clock signal signals into which the reference clock signal is distributed so as to reach at the same time said plurality of phase comparators, are set as the other inputs of said phase comparators.